1. Field of the Invention
This invention relates generally to the methods and structures of providing semiconductor devices and more particularly to such structure and method of providing a semiconductive matrix of a plurality of silicon oxide silicon (SOS) transistor-memory elements disposed on a semiconductor chip.
2. Description of the Prior Art
Field effect transistor integrated memory devices and processes for the fabrication thereof are well known at this time. The commonly assigned Dennard U.S. Pat. No. 3,387,286 discloses such circuits and methods of making the same. Although the teachings of the Dennard patent have been available for many years, a memory cell of such simplicity has not been commercially exploited until recently when process technology has become more adequately understood and processing techniques and methods developed to a point of making commercial exploitation of said devices economical.
U.S. Pat. No. 3,841,926 of Garnache et al. teaches a method for fabricating integrated circuits of high density wherein is provided a process which allows the use of multiple conducting layers in a dielectric above the semiconductor substrate having diffused areas of opposite conductivity type and utilizing polycrystalline silicon (polysilicon) dually as a field shield and a capacitor plate. Semiconductor devices of the character heretofore referred to are generally MNOS type wherein a composite dielectric is utilized e.g. silicon dioxide and silicon nitride. This type of structure exhibits certain undesirable conditions which make the device inefficient, and impractical for use in a memory array. These conditions are such as electron injection into the interface area of the dual dielectric which causes the device to be partially operative in an off condition. Likewise, the gate and edge abutting, for example a polysilicon field shield will accumulate electrons believed due to field variations causing a difference in threshold voltage requirements between the center portion and the end portion of the gate area.
A structure of the type (MNOS) described above is illustrated in U.S. Pat. No. 3,925,804 to Cricchi. U.S. Pat. No. 3,893,160 to Botzenhardt discloses a resistive connecting contact for a silicon semiconductor component comprising, on a semiconductor body, a layer sequence including a metallic silicide in composite form with other metals such as titanium-molybdenum-gold. The disclosure also contains a description of the method for making such a contact.
The use of aluminum-copper conducting contact metal is described and shown in U.S. Pat. No. 3,879,840. In U.S. Pat. No. 3,858,304 a process is disclosed for fabricating small geometry semiconductor devices wherein an active region or regions are formed in a semiconductor layer and metallization patterns are formed on the surface thereof, while a photoresist pattern which is used to define the geometry of these regions and patterns is left temporarily in place between metal and semiconductor. Subsequently, the resist is lifted off, the surface of the oxide located between the metal and semiconductive layer and whose geometry it controlled and carrying with it the metallization lying on the resist surface and leaving narrow strips of metallization in contact with the active regions.
In U.S. Pat. No. 3,777,364 a metal silicide is used to form an interconnect layer of conductive material on a semiconductor device. This disclosure teaches the forming of a platinum silicide on a polycrystalline silicon material which adheres to the underlying oxide. This is accomplished by combining the platinum and the polycrystalline silicon by heating to about 850.degree. C.
U.S. Pat. No. 3,740,835 discloses a semiconductor device contact made by depositing a layer of semiconductor material in a contact opening of an insulating mask, metallizing and heating to bond the metal to the layer of semiconductor material and to the original device surface for permitting greater ease of contacting shallow junctions.